By packaging different chips together, connected through an interposer or through-silicon via, those signals can be speeded up using shorter wire distances and wider conduits.ģ. Shrinking features and adding more functionality onto semiconductors requires longer and thinner wires, which increases the time it takes for signals to move around a chip. Being able to shrink just the digital portions and keep analog at older process geometries is increasingly attractive, but it also requires some sophisticated communication between dies.Ģ. Analog IP doesn’t shrink as easily as digital circuits from one process node to the next, making it extremely time-consuming and costly to move IC designs from one process node to the next in accordance to Moore’s Law. There are several key drivers for these changes:ġ. While SiP saw limited adoption in its earliest forms, there has been much work done on improving this concept recently with 2.5D and 3D-ICs, as well as package-on-package and flip-chips.
Connections historically have been through wire bonds. Rather than put chips on a printed circuit board, they can be combined into the same package to lower cost or to shorten distances that electrical signals have to travel.
SiP has been around since the 1980s in the form of multi-chip modules. This is in contrast to a system on chip, or SoC, where the functions on those chips are integrated onto the same die. A system in package, or SiP, is a way of bundling two or more ICs inside a single package.
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